1. Field of the Invention
The present invention relates to the field of fabricating semiconductor devices, such as MOS transistors, requiring thin oxide layers formed on a semiconductor surface to electrically insulate the semiconductor surface from an electrically active region, such as a gate electrode, formed over the semiconductor surface.
2. Description of the Related Art
The dimensions of modem integrated circuits are steadily shrinking, while at the same time providing both improved device performance and circuit density. Both advantages are mainly obtained by steadily shrinking the feature sizes of the individual semiconductor devices, such as MOS transistors, whereby critical dimensions, i.e., minimum feature sizes that can be reproducibly printed onto the substrate, are currently approaching the 0.1 μm range. The formation of modem ultra high-density integrated circuits requires 500 process steps or more, wherein one of the most critical steps is the formation of the gate electrode of the transistors. The gate electrode controls, upon application of a suitable control voltage, for example 2-3 V, the current flow through a channel that forms below a thin gate oxide layer separating the gate electrode from the underlying semiconductor region. The lateral dimension of the gate electrode, along which the highly doped source and drain regions are separated by the channel region, significantly affects the device performance with respect to signal propagation time and current flow from the source to the drain. Trimming this lateral gate dimension, also referred to as gate length, down to a size of about 0.1 μm necessitates an enormous effort to establish an appropriate photolithography technique and sophisticated etch trim method.
The reduction of the gate length is, however, only one aspect to accomplish improved device performance. Another important factor in scaling down the feature sizes of a MOS transistor to obtain superior device characteristics is the provision of a sufficiently thin oxide layer that electrically insulates the gate electrode from the underlying channel region. The reason for this is that for a given set of voltages applied to the terminals of the transistor, such as the drain/source voltage and the gate voltage, the drain current is inversely proportional to the thickness of the gate oxide layer. Accordingly, to obtain superior device performance, it is essential to minimize the thickness of the gate oxide, while, at the same time, insuring that the gate oxide layer exhibits long-term reliability and does not break down during operations. For example, while a typical thickness of an advanced gate oxide layer in 1990 was in the range of about 20-25 nm, the thickness of a gate oxide layer of sophisticated MOS transistors in modem CPUs is today in the range of about 2-3 nm. On the other hand, the operating voltage applied to the gate electrode during operation of the device has only been reduced by a factor of approximately 2-3, compared to a factor of approximately 6-7 for the thickness of the gate oxide layer. Thus, the voltage per length, i.e., the electrical field across the gate oxide, has become significantly larger in modem integrated circuits. Therefore, the intrinsic reliability of the gate oxide layer, i.e., the robustness of the gate oxide layer against leakage current, charge carrier accumulation and electrical breakdown, significantly determines the maximum gate voltage allowed for a given target product lifetime. Thus, one of the most significant challenges for process engineers is to provide a sophisticated process technique that results in uniform and reproducibly high quality gate oxide layers exhibiting a layer thickness of only a few atomic layers.
One important factor adversely affecting the quality of a thin gate oxide layer is the out-diffusion of dopant ions injected into the semiconductor substrate to define the active region in which the transistor is to be formed. The active region is also denoted as p-well or n-well depending on the type of MOS transistor. This out-diffusion occurs due to the elevated temperatures during various heat treatments necessary to, for example, cure implantation-induced damage caused during ion implantation of the dopant ions. Since each heating process of the substrate significantly accelerates the process of diffusion of the dopant ions, which will finally blur the required profile of the dopant concentration within the active regions, a so-called thermal budget of the substrate may not exceed a specified design value that depends on operating conditions of the device and on the targeted lifetime of the device. The thermal budget can be quantified as the area under a time-diffusivity (t-D) curve, wherein the diffusion activity of the dopants in the semiconductor are shown depending on the time for which the diffusion has taken place. As the diffusivity is a function of temperature to which the substrate is exposed during the various process steps, an optimum performance and lifetime is obtained only when the thermal budget is minimized. The t-D curve not only represents the temperature dependence of the diffusion activity of the dopants, but also includes the activation energy for the different processes. As a consequence, the reliability of a thin gate oxide layer formed in the vicinity of doped semiconductor regions is significantly affected by dopant atoms diffused in the vicinity or into the gate oxide layer during various process steps, and, in particular, during annealing of the substrate to reduce implantation-induced damage in the substrate. Moreover, the presence of crystalline defects in the vicinity of the gate oxide layer that may possibly be generated by ion-implantation and that are not sufficiently repaired by heating the substrate, also significantly contributes to the reliability of the gate oxide. These defects may act as scattering centers for charge carriers during operation of the device and may inject an increased number of charge carriers into the gate oxide layer. Furthermore, these crystalline defects may adversely influence the growth of the oxide layer, with respect to the quality of the oxide, since the required thickness of the gate oxide layer is only a few atomic layers.
Accordingly, there exists a need for an improved method of forming a thin oxide layer on a semiconductor surface comprising a doped region.